1. Field of the Invention
The present invention relates to a solid state image pickup device and a method for manufacturing the same.
2. Related Background Art
As the representative structures of the solid state image pickup device, there are known a CCD sensor consisting of photodiodes and CCD shift registers, and a CMOS sensor such as APS (active pixel sensor) consisting of photodiodes and MOS transistors.
The APS is provided, in each pixel, with a photodiode, an MOS switch, an amplifier circuit for amplifying the signal from the photodiode etc., and has various advantages of enabling XY addressing and single-chip integration of the sensor and the signal processing circuit. On the other hand, because of a larger number of elements in each pixel, the APS is associated with a smaller pixel aperture rate and difficulty in reducing the chip size which determines the dimension of the optical system, and, for these reasons, the majority of the commercially available solid state image pickup devices is represented by the CCD.
However, the CMOS sensor is recently attracting attention, because of the progress in the technology for size reduction of the MOS transistors and the increasing demand for the single-chip integration of the sensor and the signal processing circuit and for the lower electric power consumption.
FIG. 1 is an equivalent circuit diagram of a pixel region of the conventional APS and a solid state image pickup device utilizing the same, as reported by Eric R. Fossum et al. at the 1995 IEEE Work Shop. In the following there will be briefly explained the configuration of the prior technology.
The photoelectric conversion unit is composed of a buried photodiode of the type employed in the CCD. The buried photodiode with a surfacially highly doped p-layer can suppress the dark current generated at the SiO2 surface, and there can also be formed a junction capacitance between the n-layer in the accumulation unit and the surfacial p-layer, thereby increasing the saturation charge amount of the photodiode.
A photo-induced signal charge Qsig accumulated in a photoelectric conversion unit (photodiode) PPD is transferred, through a transfer unit TX consisting of a MOS transistor, to a floating diffusion region FD.
The signal charge Qsig is converted by the capacitance CFD of the floating diffusion region into a voltage Qsig/CFD, which is read through a source follower circuit.
In such prior technology, however, since the n-layer constituting the charge accumulation region is separated from the surface, it is necessary, in order to read the charge from such charge accumulation region to the floating diffusion region, to apply a voltage higher than in the ordinary MOS transistor to the control electrode of the MOS transistor employed in the transfer unit (transferring MOS transistor).
FIG. 5 shows the potentials of the channel region in a conventional MOS transistor and the transferring MOS transistor. In FIG. 5, the light enters from the left-hand side, and, on the right-hand side there are formed in succession a transparent insulation layer such as of SiO2 or SiN, a highly doped p-layer and an n-layer constituting the photodiode. The curve shows changes in the potential level under the voltage application. In FIG. 5, there are shown an oxide layer 301, Fermi level 302 of the n-layer of the photodiode, Fermi level 303 of a bypass region, a potential 304 under the application of a threshold voltage of the present invention, and a potential 305 under the application of the threshold voltage of the prior technology.
As indicated by a broken line in FIG. 5., the potential has to be varied larger since the n-layer is separated from the surface.
The threshold voltage Vth of the conventional MOS transistor is given by the following equation:
      V    th    =                                                                        2                ⁢                                                                  ⁢                                  ϕ                  F                                            +                              V                S                                      )                    *          2          ⁢                      ɛ            Si                    *                      qN            sub                                      C        OX              +          2      ⁢              ϕ        F              +          V      S        +          V      FB      wherein:
φ: Fermi potential
Vs: substrate bias
∈si: dielectric constant of Si
q: charge amount of electron
Nsub: substrate impurity concentration
VFB: flat band voltage
COX: parasite capacitance of floating diffusion region.
On the other hand, the threshold voltage Vth of the transfer MOS transistor for transfer from the buried photodiode is given by the following equation, wherein Xj is the junction depth of the surfacial p-layer of the photodiode:
            V      th        =                                                                      (                                                      2                    ⁢                                          ϕ                      F                                                        +                                      V                    S                                                  )                            *              2              ⁢                              ɛ                Si                            *                              qN                sub                                                          C            OX                          *        A            +                        (                                    2              ⁢                              ϕ                F                                      +                          V              S                                )                *                  A          2                    +              V        FB                  A    =          1      +                        X          j                                                                    (                                                      2                    ⁢                                          ϕ                      F                                                        +                                      V                    S                                                  )                            *              2              ⁢                              ɛ                Si                                                    qN              sub                                          
Since the difference of the two becomes larger as the impurity concentration in the substrate becomes higher, the charge reading becomes more difficult with the increase in the impurity concentration of the substrate in case of a finer geometry of the elements.
More specifically, under the conditions of an oxide layer thickness of 15 nm and an impurity concentration of 8×1016 cm−3 in the p-type well, the threshold voltage of the ordinary MOS transistor is about 0.7 V while that of the buried source becomes as high as 5.0 V. In the prior art, it becomes impossible to read almost all the change from the photodiode with the increase in the threshold voltage. As a result, the charge remains in the photodiode, thus forming a retentive image or a noise, thus significantly deteriorating the image quality.